1. Field of the Invention
The present invention relates to silicon metal oxide semiconductor field effect transistor (MOSFET), and to a method of forming a metal silicide contacts to the Si MOSFET.
2. Description of the Related Art
Metal oxide silicon semiconductor field effect transistor (MOSFET) scaling requires the continuous reduction of the gate length. When the MOSFET channel is made short, the device threshold voltage, Vt, becomes dependent on the gate length. The effect, known as the “short channel effect (SCE)”, must be circumvented or otherwise devices with different gate lengths would have a different turn-on voltage. Since a variance in the gate length is always expected due to production tools tolerance, the dependency of Vt on the gate size may cause the circuits to fail.
To suppress SCE, a scaling of the silicon-on-insulator (SOI) film thickness is needed. As shown below, the design of a device with a shorter gate length would require the use of a thinner SOI channel. Moreover, this design rule holds for both a single gate MOSFET and a double gate MOSFET.
That is, FIG. 1 shows the change in Vt as a function of the gate length for different SOI channel thicknesses (tsi). Specifically, FIG. 1 shows that when a very short gate length is produced, instead of obtaining a very flat Vt, a sharp roll-off of Vt is shown. It is noted that, in any given manufacturing, there is always some tolerance since it is not possible to print exactly the same from wafer-to-wafer and even from device-to-device on the same wafer. Hence, in fact there will be some tolerance (e.g., 10% variation in gate length across the wafer). If such a tolerance/variance is made on the flat region of the plot of the gate length of FIG. 1, no problem should arise.
However, if such a 10% gate length variation occurs on the sloping portion of FIG. 1, then a problem may occur in that there will be a great difference in the threshold voltage (Vt) of devices across the wafer. That is, some devices on the wafer may begin conducting at lower voltages, whereas other devices would begin conducting at higher voltages. Thus, the circuit may not work and FIG. 1 shows the importance of controlling the gate length. Hence, some problems may arise as technology progressing to very short gate lengths.
Further, it is noted that in FIG. 1, both single and double gate MOSFETs show an improved SCE behavior when a thinner channel is used. However, making the SOI channel thinner imposes a new challenge. That is, as the channel is made thinner, the series resistance to the source and drain increases. The parasitic series resistance can affect the speed of the device, and therefore must be minimized. To reduce the resistance, the source and drain regions are thickened. An optimized device would have a thin channel region for suppression of SCE, and thick source and drain regions for low series resistance. Making the source and drain thicker may be achieved by selective epitaxy, but that would add silicon only to the source, drain and gate regions.
FIG. 2A illustrates a MOSFET structure with a “thickened” silicon source and drain 8 by epitaxy. Specifically, FIG. 2A shows a silicon substrate 1, having a buried oxide layer 2 formed thereon. A silicon-on-insulator (SOI) layer 3 is formed on the BOX layer 2. A gate dielectric 4 is formed on the SOI 3, with a gate 5 being formed on the gate dielectric 4. Gate spacers 6 are also provided on sidewalls of the structure. The Si epitaxy must be selective or otherwise silicon will be deposited on the device gate spaces 6 which would short the source and drain to the gate.
However, selective silicon epitaxy usually requires high growth temperatures (e.g., about 850-1200° C.), and is very sensitive to surface preparation (especially cleaning), which makes it a volatile technique for production. Indeed, the process is highly selective such that the surface chemistry becomes extremely important. For example, if there is a small amount of oxide such as a native oxide or the like which remains on the surface, there will be no growth at those areas, thereby making the yield very poor.
A simpler and more robust technique to contact the thin SOI channel is by forming silicon sidewall contacts to the source and drain, as described in T. Yoshitomi, M. Saito, T. Ohguro, M. Ono, H. S. Momose, and H. Iwai, “Silicided Silicon-sidewall Source and Drain Structure for High Performance 75-nm Gate Length pMOSFETs,” 1995 Symposium on VLSI Technology Digest, page 11 (e.g., Ref. 1). This method was also shown to be very useful also in the case of double gate MOSFET structures, as described in U.S. Pat. No. 5,773,331, to P. M. Solomon et al. entitled “Method for Making Single and Double Gate Field Effect Transistors with Sidewall Source Drain Contacts”, and incorporated herein by reference (e.g., Ref. 2).
This method includes depositing a silicon film (e.g., poly-Si) and etching it with a directional etcher (e.g., such as reactive ion etching (RIE)) to form Si sidewalls on either side of the gate. The sidewall forms an extension of the source and the drain on which metal contacts can be later formed.
FIG. 2B illustrates a typical MOSFET structure with silicon source and drain sidewalls 7. The sidewall technique does not require a selective deposition and the deposition temperature can be relatively low (e.g., such as lower than approximately 700° C. depending upon the gas precursor used; for example, silane (SiH4) can be used at approximately 460° C. but has poor selectivity). Moreover, the deposited silicon can be re-crystallized (i.e., by using the thin SOI as a seed) using a rapid thermal anneal (RTA).
To make low resistance contacts, the use of a silicide is required, regardless of the source and drain structure (e.g., sidewall or epitaxially grown). The conventional self-aligned silicide process (salicide) used for planar source and drain must be modified in the case of a silicon sidewall source and drain. However, a direct application of the standard salicide process to the sidewall source and drain shows the following problems.
First, as illustrated in FIG. 3, reduction of the contact area occurs due to the Si consumption by the suicide reaction, which increases the series resistance. That is, the left-hand Si sidewall in FIG. 3 has been mostly converted into CoSi2. The resulting contact are, Ac2 is therefore reduced compared to the contact areas Ac1, before anneal.
Secondly, as shown in the schematic of FIG. 4 and the associated transmission electron micrograph (TEM), encroachment of the silicide into the Si channel occurs. The problem arises due to an infinite reservoir of metal at the base of the sidewall. While the metal reaction with the silicon sidewall is self-limited due to the finite thickness of the metal covering the sidewall, the supply of metal at the base of the sidewall is not limited. Thus, encroachment of the channel occurs. The TEM shows a dark region and a lighter region (and a clear boundary therebetween) of the channel region. The dark region represents the silicide encroaching into the channel under the gate. This encroachment is highly undesirable and leads to faulty device operation/failure.
Another problem shown in FIG. 4 is that the sidewalls are of unequal size and shape. That is, the left sidewall has been diminished as compared to the right sidewall. Generally, it is desirable to have as large a surface area for the sidewall as possible, since this is the contact area. The larger the contact area, the lower the resistivity the device will have. Hence, a method is desirable which consumes as little of the sidewall as possible. Thus, ideally, the sidewalls before annealing would have substantially the same size/shape as after the annealing. However, prior to the present invention, such a technique has not been developed.